Using Hierarchy in Design Automation: The Fault Collapsing Problem

Although the problem of fault collapsing is not considered to be too complex, the time of collapsing faults in large circuits can be several hours or more. Large circuits are efficiently described using hierarchy, which significantly helps the architectural design, verification and physical design. We add fault collapsing to that list. We do not flatten the circuit and the collapsed fault sets computed once for sub-circuits are reused for all instances of those sub-circuits. The CPU time for collapsing faults in a flattened 128-bit array multiplier, which is about 8 hours, can be brought down to 40 seconds by using multiple levels of hierarchy. Additionally, by applying the exponential-complexity functional fault collapsing only to smaller sub-circuits, hierarchical collapsing in large circuits results in collapse ratios lower than those obtained with structural collapsing of flattened circuits. Using functional collapsing for a few small library cells, we hierarchically collapse faults in the 128-bit multiplier to sets of 480,757 equivalence and 265,824 dominance collapsed faults. In comparison, the flattened circuit collapses into 712,208 and 534,284 equivalence and dominance collapsed fault sets, respectively. We observe that the CPU time for fault collapsing for Boolean circuit by conventional programs grows as the square of the circuit size. A closer to linear time complexity can be expected for hierarchical fault collapsing.